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Cameroon GCE A-Level Computer Science (0795) Practice Questions - Cameroon General Certificate of Education Advanced Level Computer Science (Syllabus 0795) Exam

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About this Exam

Prepare with the Cameroon GCE A-Level Computer Science (0795) Practice Questions - Cameroon General Certificate of Education Advanced Level Computer Science (Syllabus 0795) Exam practice quiz. This question bank includes 100 questions covering memory, standard, address, binary, and software. Use it to review important concepts, identify knowledge gaps, and build confidence for the related exam, course, or assessment.

Sample Questions

Question 1
In computer processor architecture, what is the defining structural difference between the Harvard architecture and the Von Neumann architecture?
Harvard architecture uses physically separate memory units and buses for instructions and data, whereas Von Neumann uses unified memory and buses for both.
Von Neumann architecture utilizes separate arithmetic pipelines for integer and floating-point operations, whereas Harvard combines them.
Harvard architecture requires all instructions to execute in a single clock cycle, whereas Von Neumann uses multi-cycle microcode.
Von Neumann architecture uses direct-mapped caches exclusively, whereas Harvard architecture supports fully associative caches.
Question 2
During the CPU fetch-decode-execute cycle, what is the primary role of the Program Counter (PC)?
It holds the current machine instruction being decoded and executed by the Control Unit.
It stores the memory address of the next instruction to be fetched and executed.
It records arithmetic status flags such as zero, carry, sign, and overflow resulting from ALU operations.
It temporarily stores operand data transferred between main memory and the Arithmetic Logic Unit.
Question 3
During a memory read operation in the fetch cycle, how do the Memory Address Register (MAR) and Memory Data Register (MDR) interact with the system buses?
MAR places data onto the data bus while MDR receives the target address from the address bus.
MAR holds the address placed onto the address bus, while MDR latches the data returned from memory via the data bus.
MAR decodes the operation code while MDR sends control signals over the control bus to synchronize RAM.
Both MAR and MDR send parallel 64-bit addresses over the address bus to achieve interleaved memory access.
Question 4
In a standard accumulator-based CPU architecture, which sequence of Register Transfer Level (RTL) micro-operations correctly represents the instruction fetch phase?
MAR <- [PC]; PC <- [PC] + 1; MDR <- Memory[MAR]; CIR <- [MDR]
MDR <- [PC]; MAR <- [MDR]; CIR <- Memory[MAR]; PC <- [PC] + 1
CIR <- [PC]; MAR <- [CIR]; MDR <- Memory[MAR]; PC <- [MDR]
MAR <- [ACC]; MDR <- Memory[MAR]; PC <- [PC] + 1; CIR <- [MDR]
Question 5
A processor has a 32-bit address bus and byte-addressable physical memory. What is the maximum physical memory capacity that this processor can directly address?
512 Megabytes (512 MB)
2 Gigabytes (2 GB)
4 Gigabytes (4 GB)
16 Gigabytes (16 GB)

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Additional Information

Cameroon GCE A-Level Computer Science (0795) Practice Questions - Cameroon General Certificate of Education Advanced Level Computer Science (Syllabus 0795) Exam

This practice set contains 100 questions from the matching question bank and focuses on memory, standard, address, binary, and software. Work through each question carefully, review the provided solutions, and revisit topics that need more study before your next attempt.

This is an independent study resource intended for practice and review; it is not an official examination or an endorsement by any organization named in the title.

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Frequently Asked Questions

This quiz contains a total of 100 practice questions carefully selected to test your knowledge on this subject.
Yes, you will have exactly 0 minutes to complete the exam. A countdown timer will be visible once you start.
Yes, you can retake this practice test as many times as you need. The questions and options may be randomized on subsequent attempts to ensure comprehensive learning.

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